| FreeRunner is currently in active development; certain things may change. |
FreeRunner
| Information | |
|---|---|
| Founder(s) | ArminAustin200 |
| Contribution(s) | ArminAustin200 - PCB Design/Firmware Modification
Octal450 - Timing Files DrTrinity - General guidance/Help creating MAXV compatible urJTAG files |
| Purpose | Altera MAX V-based Glitch Chip |
| GitHub | https://github.com/ArminAustin200/FreeRunner |
FreeRunner is an open-source Glitch Chip created by ArminAustin200. It is based on the Altera MAX V CPLD as a modern replacement to Xilinx-based Glitch Chips, which have since reached EOL.
Features
- RGH1.2 support for Falcon, Jasper, Tonasket, and Trinity consoles is implemented. Support for Corona is being worked on.
- Multi-NAND support for dual-booting on both phat and slim consoles.
- EXT_CLK support for Xenon/Zephyr consoles.
Install Diagrams
| Method | Xenon/Zephyr | Falcon/Opus | Elpis | Jasper | Tonasket | Trinity | Corona | Waitsburg/Stingray |
|---|---|---|---|---|---|---|---|---|
| EXT_CLK | OK! | X | X | X | X | X | X | X |
| RGH1.2 | X | OK! | OK! | OK! | OK! | OK! | OK! * | OK! * |
| Multi-NAND | X | OK! | OK! | OK! | OK! | OK! | OK! * | OK! * |
*: Oscillator required
- NOTE: Multi-NAND WILL NOT WORK with EXT_CLK as there is not enough space on the CPLD to fit the logic for EXT_CLK & XSB mux-ing
Phat
Falcon/Jasper/Tonasket (RGH1.2)
- A - PLL
- B - STBY_CLK
- C - POST
- D - RST
Xenon/Zephyr (EXT_CLK)
- A - EXT_CLK
- B - STBY_CLK
- C - POST
- D - RST


Slim
Trinity (RGH1.2)
- F - PLL (For slim)
- B - STBY_CLK
- C - POST
- E - RST (For slim)
Corona/Waitsburg/Stingray (RGH1.2)
- F - PLL (For Slim)
- C - POST (requires POSTFIX)
- E - RST (For Slim)
Phat Multi-NAND
- Info and diagrams coming soon...
Slim Multi-NAND
In order to do a multi-NAND install with FreeRunner on a slim console (Trinity/Corona/Waitsburg/Stingray), a NAND-wich install must be done. For the CE lines of the NAND-wich, the pads labelled TP1 to TP10 (NOTE: some limited edition versions of FreeRunner have up to 10 test points, while most have 5) must be used.
NAND CE Lines
- CE1 - TP1
- CE2 - TP2
- CE3 - TP3
- ...
Repeat this for however many NANDs as you intend on using.
Credits
- ArminAustin200 (Design and Development)
- Octal450 (Assistance, Base for timing files/Multi-NAND logic)
- DrTrinity (Assistance)
